;*********************************************************************** ; File Name: f240regs.h ; Originator: Texas Instruments ; ; Description: F240 header file containing all peripheral register ; declarations as well as other useful definitions. ; ; Last Updated: 27 May 1997 ; ;*********************************************************************** ; On Chip Periperal Register Definitions (All registers mapped into data ; space unless otherwise noted) ;----------------------------------------------------------------------- ;C2xx Core Registers IMR .set 0004h ;Interrupt Mask Register GREG .set 0005h ;Global memory allocation Register IFR .set 0006h ;Interrupt Flag Register ;System Module Registers SYSCR .set 07018h ;System Module Control Register SYSSR .set 0701Ah ;System Module Status Register SYSIVR .set 0701Eh ;System Interrupt Vector Register ;Watch-Dog(WD) / Real Time Int(RTI) / Phase Lock Loop(PLL) Registers RTICNTR .set 07021h ;RTI Counter Register WDCNTR .set 07023h ;WD Counter Register WDKEY .set 07025h ;WD Key Register RTICR .set 07027h ;RTI Control Register WDCR .set 07029h ;WD Control Register CKCR0 .set 0702Bh ;Clock Control Register 0 CKCR1 .set 0702Dh ;Clock Control Register 1 ;Analog-to-Digital Converter(ADC) registers ADCTRL1 .set 07032h ;ADC Control Register 1 ADCTRL2 .set 07034h ;ADC Control Register 2 ADCFIFO1 .set 07036h ;ADC Data Register FIFO1 ADCFIFO2 .set 07038h ;ADC Data Register FIFO2 ;Serial Peripheral Interface (SPI) Registers SPICCR .set 07040h ;SPI Configuration Control Register SPICTL .set 07041h ;SPI Operation Control Register SPISTS .set 07042h ;SPI Status Register SPIBRR .set 07044h ;SPI Baud Rate Register SPIEMU .set 07046h ;SPI Emulation buffer Register SPIBUF .set 07047h ;SPI Serial Input Buffer Register SPIDAT .set 07049h ;SPI Serial Data Register SPIPC1 .set 0704Dh ;SPI Port Control Register 1 SPIPC2 .set 0704Eh ;SPI Port Control Register 2 SPIPRI .set 0704Fh ;SPI Priority control Register ;Serial Communications Interface (SCI) Registers SCICCR .set 07050h ;SCI Communication Control Register SCICTL1 .set 07051h ;SCI Control Register 1 SCIHBAUD .set 07052h ;SCI Baud Select register, high bits SCILBAUD .set 07053h ;SCI Baud Select register, high bits SCICTL2 .set 07054h ;SCI Control Register 2 SCIRXST .set 07055h ;SCI Receive Status Register SCIRXEMU .set 07056h ;SCI Emulation data buffer Register SCIRXBUF .set 07057h ;SCI Receiver data buffer Register SCITXBUF .set 07059h ;SCI Transmit data buffer Register SCIPC2 .set 0705Eh ;SCI Port Control Register 2 SCIPRI .set 0705Fh ;SCI Priority Control Register ;External Interrupt Registers XINT1CR .set 07070h ;Interrupt 1 Control Register NMICR .set 07072h ;Non-maskable Interrupt Control Register XINT2CR .set 07078h ;Interrupt 2 Control Register XINT3CR .set 0707Ah ;Interrupt 3 Control Register ;Digital I/O OCRA .set 07090h ;Output Control Reg A OCRB .set 07092h ;Output Control Reg B PADATDIR .set 07098h ;I/O port A Data & Direction reg. PBDATDIR .set 0709Ah ;I/O port B Data & Direction reg. PCDATDIR .set 0709Ch ;I/O port C Data & Direction reg. ;General Purpose Timer Registers - Event Manager (EV) GPTCON .set 7400h ;General Purpose Timer Control Register T1CNT .set 7401h ;GP Timer 1 Counter Register T1CMPR .set 7402h ;GP Timer 1 Compare Register T1PR .set 7403h ;GP Timer 1 Period Register T1CON .set 7404h ;GP Timer 1 Control Register T2CNT .set 7405h ;GP Timer 2 Counter Register T2CMPR .set 7406h ;GP Timer 2 Compare Register T2PR .set 7407h ;GP Timer 2 Period Register T2CON .set 7408h ;GP Timer 2 Control Register T3CNT .set 7409h ;GP Timer 3 Counter Register T3CMPR .set 740Ah ;GP Timer 3 Compare Register T3PR .set 740Bh ;GP Timer 3 Period Register T3CON .set 740Ch ;GP Timer 3 Control Register ;Full & Simple Compare Unit Registers - Event Manager (EV) COMCON .set 7411h ;Compare Control Register ACTR .set 7413h ;Full Compare Action Control Register SACTR .set 7414h ;Simple Compare Action Control Register DBTCON .set 7415h ;Dead-band Timer Control Register CMPR1 .set 7417h ;Full Compare Unit 1 Compare Register CMPR2 .set 7418h ;Full Compare Unit 2 Compare Register CMPR3 .set 7419h ;Full Compare Unit 3 Compare Register SCMPR1 .set 741Ah ;Simple Compare Unit 1 Compare Register SCMPR2 .set 741Bh ;Simple Compare Unit 2 Compare Register SCMPR3 .set 741Ch ;Simple Compare Unit 3 Compare Register ;Capture & QEP Registers - Event Manager (EV) CAPCON .set 7420h ;Capture Control Register CAPFIFO .set 7422h ;Capture FIFO Status Register CAP1FIFO .set 7423h ;Capture 1 Two-level deep FIFO Register CAP2FIFO .set 7424h ;Capture 2 Two-level deep FIFO Register CAP3FIFO .set 7425h ;Capture 3 Two-level deep FIFO Register CAP4FIFO .set 7426h ;Capture 4 Two-level deep FIFO Register ;Interrupt Registers - Event Manager (EV) EVIMRA .set 742Ch ;EV Interrupt Mask Register A EVIMRB .set 742Dh ;EV Interrupt Mask Register B EVIMRC .set 742Eh ;EV Interrupt Mask Register C EVIFRA .set 742Fh ;EV Interrupt Flag Register A EVIFRB .set 7430h ;EV Interrupt Flag Register B EVIFRC .set 7431h ;EV Interrupt Flag Register C EVIVRA .set 7432h ;EV Interrupt Vector Register A EVIVRB .set 7433h ;EV Interrupt Vector Register B EVIVRC .set 7434h ;EV Interrupt Vector Register C ;Flash Module Registers (mapped into Program space) SEG_CTR .set 0h ;Flash Segment Control Register WADRS .set 2h ;Flash Write Address Register WDATA .set 3h ;Flash Write Data Register ;Wait State Generator Registers (mapped into I/O space) WSGR .set 0FFFFh ;Wait State Generator Register ;----------------------------------------------------------------------- ; Constant Definitions ;----------------------------------------------------------------------- ;Data Memory Boundary Addresses B0_SADDR .set 00200h ;Block B0 start address B0_EADDR .set 002FFh ;Block B0 end address B1_SADDR .set 00300h ;Block B1 start address B1_EADDR .set 003FFh ;Block B1 end address B2_SADDR .set 00060h ;Block B2 start address B2_EADDR .set 0007Fh ;Block B2 end address XDATA_SADDR .set 08000h ;External Data Space start address XDATA_EADDR .set 09FFFh ;External Data Space end address ;Frequently Used Data Pages DP_0 .set 0 ;page 0 of data space DP_PF1 .set 224 ;page 1 of peripheral file (7000h/80h) DP_PF2 .set 225 ;page 2 of peripheral file (7080h/80h) DP_PF3 .set 226 ;page 3 of peripheral file (7100h/80h) DP_EV .set 232 ;page 1 of EV reg file (7400h/80h) ;Bit codes for Test Bit instruction (BIT) BIT15 .set 0000h ;Bit Code for 15 BIT14 .set 0001h ;Bit Code for 14 BIT13 .set 0002h ;Bit Code for 13 BIT12 .set 0003h ;Bit Code for 12 BIT11 .set 0004h ;Bit Code for 11 BIT10 .set 0005h ;Bit Code for 10 BIT9 .set 0006h ;Bit Code for 9 BIT8 .set 0007h ;Bit Code for 8 BIT7 .set 0008h ;Bit Code for 7 BIT6 .set 0009h ;Bit Code for 6 BIT5 .set 000Ah ;Bit Code for 5 BIT4 .set 000Bh ;Bit Code for 4 BIT3 .set 000Ch ;Bit Code for 3 BIT2 .set 000Dh ;Bit Code for 2 BIT1 .set 000Eh ;Bit Code for 1 BIT0 .set 000Fh ;Bit Code for 0 ;Bit masks used by the CBIT & SBIT Macros B15_MSK .set 8000h ;Bit Mask for 15 B14_MSK .set 4000h ;Bit Mask for 14 B13_MSK .set 2000h ;Bit Mask for 13 B12_MSK .set 1000h ;Bit Mask for 12 B11_MSK .set 0800h ;Bit Mask for 11 B10_MSK .set 0400h ;Bit Mask for 10 B9_MSK .set 0200h ;Bit Mask for 9 B8_MSK .set 0100h ;Bit Mask for 8 B7_MSK .set 0080h ;Bit Mask for 7 B6_MSK .set 0040h ;Bit Mask for 6 B5_MSK .set 0020h ;Bit Mask for 5 B4_MSK .set 0010h ;Bit Mask for 4 B3_MSK .set 0008h ;Bit Mask for 3 B2_MSK .set 0004h ;Bit Mask for 2 B1_MSK .set 0002h ;Bit Mask for 1 B0_MSK .set 0001h ;Bit Mask for 0 ;----------------------------------------------------------------------- ; M A C R O - Definitions ;----------------------------------------------------------------------- CBIT .macro DMA, MASK ;Clear bit Macro LACC DMA AND #(0FFFFh-MASK) SACL DMA .endm SBIT .macro DMA, MASK ;Set bit Macro LACC DMA OR #(MASK) SACL DMA .endm KICK_DOG .macro ;Watchdog reset macro LDP #00E0h ;DP-->7000h-707Fh SPLK #055h, WDKEY ;WDCNTR is enabled to be reset by next AAh SPLK #0AAh, WDKEY ;WDCNTR is reset LDP #0h ;DP-->0000h-007Fh .endm