DSP Builder v2.1.3 README File

This readme file for the DSP Builder includes information that was not
incorporated into the DSP Builder User Guide v2.1.3 and DSP Builder
Reference Manual v2.1.3.

This file contains the following information:

o  DSP Builder Contents
o  Hardware & Software Requirements
o  Installation
o  Licensing
o  Troubleshooting
o  Release History
o  Contacting Altera


DSP Builder Contents
====================

o  Libraries of Blocks Classified by Functionality
o  Design Examples
o  Documentation


Hardware & Software Requirements
================================

The following hardware and software is required to create HDL designs that use
blocks from the DSP Builder:

o  A PC running Windows 98/NT/2000/XP
o  MATLAB version 6.1 or 6.5
o  Simulink version 4.1 or 5.0
o  A VHDL synthesis tool that is fully compliant with the VHDL 93 specification
o  Quartus® II version 2.2 or higher

Notes: 

DSP Builder provides automated flows using Tcl scripts, and a manual flow.
In addition to Quartus II integrated synthesis, the automated flow supports:

o  Synplify version 7.2 or higher or LeonardoSpectrum version 2002.c or higher
o  ModelSim version 5.5 or higher


Installation
============

Refer to "Installing the DSP Builder" in the DSP Builder User Guide for detailed
installation instructions.


Licensing
=========

Before using the DSP Builder, you must request a license file from the Altera
web site at http://www.altera.com/licensing and install it on your PC. When you
request a license file, Altera e-mails you a license.dat file that enables HDL
file and Tcl script generation. If you do not have a DSP Builder license file,
you can create models with the DSP Builder blocks but you cannot generate HDL
files or Tcl scripts.

Refer to "Set Up Licensing" in the DSP Builder User Guide for detailed
instructions on installing your license.


Troubleshooting
===============

Refer to "Troubleshooting" in the DSP Builder User Guide for troubleshooting
information.

Release History
================

Version 2.1.3
---------------

- Generates a Verilog HDL testbench for simulation with a Quartus II
  Verilog Output File (.vo)
- Supports Quartus II version 3.0
- New blocks:
  o Barrel Shifter (Arithmetic library)
  o Bit Level Sum of Products (Arithmetic library)
  o FIFO (Storage library)
  o Flip Flop (Gates library)
  o Memory Delay (Storage library)
  o NOT (Gates library)
  o Round (Bus Manipulation library)
  o Saturate (Bus Manipulation library)
- New PLL option for indicating whether PLL output clocks should be
  kept internal or output to pins
- The SubSystem Builder block imports Verilog HDL files (.v) in
  addition to VHDL files for black-boxing subsystems


Version 2.1.2
---------------

- Supports the Stratix EP1S80 DSP development board 
- Enhanced Arithmetic (Counter, Pipelined Adder, Integrator, Differentiator, 
  and SOP TAP) and Gates (Decoder) blocks 
- Example designs, including CIC filter, infinite impulse response (IIR) filter, 
  and interleaver, now available from within the MATLAB Demos tab 

Version 2.1.1
---------------

- Minor bug fix

Version 2.1.0
---------------

- Support for the Cyclone and Stratix GX device families
- Support for the Stratix EP1S25 DSP Board
- New blocks
	- PLL block for multiple clock domains (Rate Change library)
	- Muti-Rate DFF block (Rate Change library)
	- Tsamp block (Rate Change library)
	- Binary Point Casting block (Bus Manipulation library)
	- State Machine block (State Machine library)
	- Divider block (Arithmetic library)
	- Butterfly block (Complex Numbers library)
- Support for Quartus II (v2.1 and higher) integrated synthesis
- Support for MATLAB version 6.5, and Simulink version 5.0
- Major bug fixes:
	- Support for an unlimited number of subsystems
	- Support for constant values greater than 32 bits
	- Enhanced design rule check and error-tracking back annotation

Version 2.0.0
-------------
-  Support for the Stratix device family
-  New DSP Builder blocks
	- Multiply Accumulate
	- Multiply Add
	- Shift Taps
	- Complex Signals: Complex AddSub, Complex Product, Complex 
	  Multiplexer, Complex Conjugate, Complex Delay, Complex Constant, 
	  Complex to Real-Imag, Real-Imag to Complex
	- SOPC Ports: Avalon Ports and Custom Instruction
	- GND and VCC
	- SignalTap Analysis and SignalTap
	- SubSystemBuilder
-  IP suppport
	- Install DSP MegaCore(R) functions that you download from the Altera
	  web site
	- DSP Builder automatically detects the new IP when you run MATLAB
-  New SignalCompiler user interface
	- Includes directory browser and a progress bar
	- Displays system information
	- Configures the DSP development boards (starter and professional) from
	  within Simulink


Version 1.0.0
-------------
- First release of the DSP Builder.

Contacting Altera
=================

Although we have made every effort to ensure that this version of the kit works
correctly, there might be problems that we have not encountered. If you have a
question or problem that is not answered by the information provided in this
readme file or the kit documentation, please contact your Altera Field
Applications Engineer or Altera Applications:

Technical Support Hotline:  (800) 800-EPLD (U.S.)
                            (408) 544-7000 (International)
World-Wide Web:             www.altera.com
                            www.altera.com/mysupport/

Last updated June 2003
Copyright (c) 2001 - 2003 Altera Corporation. All rights reserved.