;FSM.asm
;Prototype of a Finite State Machine Implementation

;The FSM has 2 outputs, a portoutput on PORTB and a bit output on PORTD6
;It has a 2 inputs which define the state transition conditions
;we just assume that these inputs are available in 2 registers

	
;Dhananjay V. Gadre
;July 10, 1999

.include "8515def.inc"

.def state_var=r20
.def X_input=r21
.def Y_input=r22
	
	.equ S0=0
	.equ S1=1
	.equ S2=3
	.equ S3=3
	.equ S4=4

.cseg
.org 0
        rjmp    RESET           ;Reset Handle
        rjmp    RESET
        rjmp    RESET
        rjmp    RESET
	
RESET: 

       ldi r16, $A0          ;Init the Stack Pointer
       out SPL, r16
       ldi r16, $0
       OUT SPH, r16

       ldi r16, 255          ;configure PORT B for all outputs
       out DDRB, r16       
       ldi r16, 0b01000000   ;configure PORTD6 as output
       out DDRD, r16       

	
;Initialize the State machine state variable and outputs
       ldi r16, $23
       out PORTB, r16
       cbi PORTD, 6
       ldi state_var, S0
       
chk_state:      rcall state_change
	        rcall gen_output
                rjmp chk_state

;*********************************************************
;STATE_CHANGE: Subroutine to determine if a change of state
;is warranted
;*********************************************************

;First check is the state are S2 or S3 which have unconditional
;transition

state_change:   cpi state_var, S2
	        brne chk_next1
	        ldi state_var, S3
	        ret
chk_next1:      cpi state_var, S3
	        brne chk_next2
	        ldi state_var, S4
	        ret
	
chk_next2:	cpi state_var, S0
	        brne chk_next3
                cpi X_input, 1
	        brne chkx_S0
                ldi state_var, S0
	        ret
chkx_S0:        cpi X_input, 0
	        breq chky_S0
	        ldi state_var, S0
	        ret
chky_S0:	cpi Y_input, 0
	        brne stay_S0
                ldi state_var, S1
	        ret
stay_S0:        ret
		       
chk_next3:      cpi state_var, S1
	        brne chk_next4
	        cpi X_input, 1
	        breq chky0_S1
                ret		;retain the same state
chky0_S1:       cpi Y_input, 0
                brne chky1_S1
	        ldi state_var, S2
	        ret
chky1_S1:       cpi Y_input, 1 
                brne goback
	        ldi state_var, S3
goback:         ret

chk_next4:      cpi state_var, S4
	        brne goback
	        cpi X_input, 0
	        brne goback
	        ldi state_var, S0
	        ret

;*********************************************************
;GEN_STATE: Subroutine to set outputs depending upon the 
;state value 
;*********************************************************
gen_state:	cpi state_var, S0
	        brne chks1
	        ldi r16, $23
                out PORTB, r16
                cbi PORTD, 6
	        ret
	
chks1:	        cpi state_var, S1          
	        brne chks2
	        ldi r16, $23
                out PORTB, r16
                sbi PORTD, 6
                ret
	
chks2:	        cpi state_var, S2          
	        brne chks3
	        ldi r16, $32
                out PORTB, r16
                sbi PORTD, 6
                ret
               
chks3:	        cpi state_var, S3          
	        brne chks4
	        ldi r16, $22
                out PORTB, r16
                cbi PORTD, 6
                ret
	
chks4:	        cpi state_var, S4          
	        brne chks5
	        ldi r16, $44
                out PORTB, r16
                sbi PORTD, 6

chks5:	        ret