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GETTING STARTED This tutorial provides information about the VeriLogger Pro software for students using the book, Digital Design, 3/e by M. Morris Mano. The examples from the book are included as text files with extension (.v). They are available for reading and use in the folder Book Examples located in the SynaptiCad install directory. There are ten folders under Book Examples, one for each section in the book where there are HDL examples, such as Sec03-9, Sec04-11, etc. The files in each section (except Sec11-19) provide the corresponding HDL example listings from the book. The files in Sec11-19 have HDL descriptions of integrated circuits used in the Laboratory Experiments of Chapter 11. The files can be read with the VeriLogger Editor or with Windows Notepad. The reader familiar with digital circuits and programming procedures can go directly to the VeriLogger Tutorial: Basic Verilog Simulation. Students learning digital circuits and the Verilog Hardware Description Language (HDL) for the first time may want to follow the procedure recommended here first. The two tutorials are available as HTML files in the CD ROM Flash display, and as MS Word files in C:\SynaptiCad\Examples_Book\Book_Tutorials. It is important to understand how the material in the book Digital Design is organized. Digital circuits are introduced in Chapters 1 through 3 with an introduction to Verilog HDL in Section 3-9. Further discussion of HDL does not occur until Section 4-11, following the study of combinational circuits. Sequential circuits are covered in Chapters 5 and 6 with corresponding HDL examples in Sections 5-5 and 6-6. Register Transfer Level (RTL) design descriptions are presented in Chapter 8. HDL problems are available at the end of the chapters. Read Section 3-9 in the book and study HDL Example 3-3. The example to be used here is HDL Example 3-3Err.v and is the same as HDL Example 3-3.v except for one syntax error that will be corrected. After you install the software, click on the SynaptiCAD icon to open a window of choices. To start the operation, click on the VeriLogger Pro icon. The VeriLogger screen appears, consisting of windows. The three windows of interest are the Project, Report, and Diagram windows. The Project window holds all the Verilog (. v) files attached to the currently active project. The Report window is used to report errors and to display results in text format. The Diagram window shows the timing diagrams that result from the simulation run. The menu bar options of interest here are the File, Project, Editor, and Simulate. The tool bar icons that will be used are the yellow compile button and the green triangle run button. If the windows are not properly aligned, go to the Window menu and click on Tile Horizontally. If the tool bar disappears, go to the Window menu and click on Show Toolbar. Now follow these basic steps to compile and simulate an existing Verilog HDL example.
Step 1: Copy the HDL Example into the Project window. Choose the Project > Add File(s) from the menu option, or right click the Project window to open a menu and select Add HDL File(s). Either of these operations opens a file dialog. Select Book Examples > Sec03-9 > Example3-3Err.v and press the open button to copy the file into the Project window.
Step 2: Compile the HDL Example and check for syntax errors. Press the yellow Compile button on the tool bar, or choose the Simulate > Build menu option. If the file has a syntax error, the status bar in the lower right corner displays "Compile Error". The errors are listed in the Report window at the Error tab together with their line number in parenthesis. (If the error in this example was corrected by a previous user, there will not be errors listed in the Report window.) Double click on the file name in the Project window, or double click on the error message (red E) in the Report window. This instructs the Editor to open and display the source code. The error in this example is in line 7 where dashes are used instead of underscores in circuit_with_delay. Change the dashes to underscores to correct the syntax error. Choose the Editor > Save HDL File menu option to save the changes and close the editor window. Compile the corrected example by pressing the yellow button. If there are no errors, the status bar in the lower right corner displays "Simulation Built". Note that one module name is surrounded by bracket << stimcrct >> to indicate that it is the top-level module. Also, note that the diagram window has input and output signals listed on the waveform display. listed on the waveform display.
Step 3: Simulate the HDL example All examples can be compiled to check for syntax errors. However, in order to simulate the project, it is necessary to include a test bench or similar stimulus in order to produce input signals for the circuit. In this example, the stimulus is the stimcrct module. Press the Run green triangle button on the tool bar, or choose the Simulate > Run menu option. The status bar in the lower right corner displays "Simulation Good", and the waveforms are displayed in the Diagram window. (If the display shows "Simulation Error", there will be an error listing in the Report window.) Maximize the diagram window to verify that the timing diagrams are the same as in Fig. 3-38 of the book. Choose File > Print Diagram menu option to print the diagram. Now restore the syntax error in the example for the next user. Open the source file by double clicking on it in the Project window or in the Window pull-down menu. Restore the dashes in line 7, and save the file with Editor > Save HDL File menu option. Close the editor window. Right click on the file in the project window and choose Remove File. The file is removed from the Project window. Choose File > Exit menu option. Messages may ask if you want to save the changes, click NO to all and exit VeriLogger. The solutions to the HDL problems at the end of the chapters can be compiled and simulated by first typing and saving each solution as an HDL file. To create a new file, click on Editor and choose New HDL File from the menu option. A window appears where the HDL description of the problem solution can be typed. Then go back to Editor and choose the menu option Save HDL File As. Enter a name for the file (it will automatically be assigned the extension .v) and save it in the Book Solutions directory (if there is such a directory in your system, otherwise, you can create a new folder with this name). Simple problems can be solved with one or two module descriptions. More complex problems or other assignments may require multiple module descriptions created separately and saved in a number of HDL files. An HDL Project combines all the HDL files into one project and is saved using a project name with an extension .hpj. A new HDL Project is created by choosing Project > New HDL Project from the menu option. The HDL files for the project are then added by choosing Project > Add HDL File menu option. For simple cases, it may be convenient to add HDL files to an untitled project. When you study Chapter 4 in the book, read Section 4-11, continue all the way to the end, and read the procedure for writing a simple test bench. As mentioned previously, in order to simulate a project it is necessary to provide a stimulus such as a test bench to produce input signals for the circuit. The simulation waveforms are displayed in the Diagram window. If the test bench includes display tasks with keywords such as $display or $monitor, the simulator produces a numeric output placed in the Report window. HDL Example 4-10 in the book shows such a numeric output. Repeat the three-step procedure discussed earlier to compile and simulate HDL Example 4-10. The HDL File is located in directory Book Examples > Sec04-11 > Example4-10.v. If no errors occur, you will find the simulation log listing of the truth table in the Report window at the verilog.log tab. It can be seen by maximizing the Report window and scrolling the text until it is visible. To print the simulation log, click on the Report menu and choose Print Report Tab. Restore the Report window and maximize the Diagram window. The waveforms can be extended by clicking on the zoom buttons (the blue circles in the tool bar). Note that D[2:0] input shows the truth table with hexadecimal numbers. Signals F1 and F2 show the timing diagram of the two outputs. Restore the Diagram window and exit by choosing File > Exit from the menu. A few messages may appear.
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