There are several tutorials shipped with all versions of Timing Diagrammer Pro, WaveFormer Pro, and TestBencher Pro. These tutorials demonstrate everything from how to draw basic timing diagrams to advanced HDL simulation techniques.

If you are running Windows, the tutorials are in the file Tutorial.chm located in the installation directory. If you are running Unix, the tutorials are in doc/tutorial under your installation directory. This file is in the new HTML Help format, which can be run by double clicking on the file name from an Explorer Window. If your system is not setup to run the new Help format, you can download the pure HTML files from this page, or print out or work through the tutorials on-line.

General Design Tutorials

• Basic Drawing and Timing Analysis (formerly Tutorial 1), explains the basic timing diagram editing environment: how to setup the base time unit and the display time unit of a timing diagram, how to draw and edit signals, delays, and setups, and how to perform time measurements. This tutorial is essential to anyone evaluating or learning to use any SynaptiCAD product.

• Simulation, Waveform Generation and Parameters (formerly Tutorial 2), covers the techniques for editing and customizing the information displayed by a parameter and its position on the screen. Also covered is: HDL simulation, virtual and group buses, and general signal manipulation. This tutorial teaches the various time-saving methods of generating waveforms using equations and other waveforms. This tutorial is essential to anyone evaluating WaveFormer Pro.

• Advanced Modeling and Simulation Tutorial (formerly Tutorial 6), demonstrates how WaveFormer Pro can quickly model and simulate a digital system of moderate complexity. You will model state machines using Boolean equations. use the Report window to find simulation errors, enter direct HDL code, model tristate gates, model n-bit gates, and call external HDL models. WaveFormer and TestBencher Pro users should do this tutorial.

Specialized Feature Tutorials

• Parameter Libraries (formerly Tutorial 3), covers the use of libraries and macro lists. This tutorial is important to do before starting a large project. Using Libraries and macro lists can save you a lot of time if they are configured properly.

• Advanced HDL Stimulus Generation Tutorial (formerly Tutorial 4), covers the basic concepts of VHDL and Verilog stimulus generation, language independent hex and binary bus translation, default mapping modes, and user defined types. WaveFormer Pro and TestBencher Pro users should do these tutorials.

• Basic Verilog Simulation (formerly Tutorial 7), covers the basic simulation features of VeriLogger Pro. This tutorial also discusses how to work create and manage projects, as well as how to build and simulate your design. VeriLogger Pro and TestBencher Pro users should perform this tutorial.

• TestBencher Pro: Basic Tutorial (formerly Tutorial 5), covers the basic concepts of using TestBencher Pro to generate bus-functional models for Verilog & VHDL. It covers Signal Properties (type, direction, vector size, and bi-directional segments), samples, parameterized state values, end diagram markers, interface diagrams, modifying top-level template files, and generating test benches. TestBencher Pro users should do this tutorial.

• TestBencher Pro: Performing a Sweep Test , covers how to use TestBencher Pro to create a global clock generator, work with cyclic timing transactions, create a sweepable delay, and create a continuous setup checker. TestBencher Pro users should perform this tutorial.

Evaluators: If you are evaluating the product we recommend that you do at least the Basic and the Advanced simulation tutorials (1,2, & 6). These will give you a good idea of the flexibility of the product. If you design in VHDL or Verilog you should also look at the HDL tutorial and the TestBencher tutorial (4 & 5).

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