Free TDML and VCD Viewer Free TDML and VCD Viewer Free TDML and VCD Viewer



Welcome to SynaptiCAD, your source for cutting edge timing analysis and VHDL & Verilog generation and simulation software! We currently offer five products: TestBencher Pro, VeriLogger Pro, WaveFormer Pro, DataSheet Pro, and Timing Diagrammer Pro.

TestBencher Pro generates reactive VHDL and Verilog test benches and bus-functional models from language-independent timing diagrams. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. An excellent tool for testing large FPGA and ASIC designs.

VeriLogger Pro is a new type of Verilog simulation environment that combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generator on the planet. Model testing is so fast in VeriLogger Pro that you can perform true bottom-up testing of every model in your design, a critical step often skipped in the race to market.

WaveFormer Pro combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator to form a groundbreaking EDA tool that should be in every digital designer’s tool kit. WaveFormer Pro allows you to automatically generate and simulate timing diagrams using common Boolean and registered logic equations. WaveFormer Pro can also import or export waveforms to VHDL, Verilog, HP's logic analyzers & pattern generators, SPICE, ABEL, and a variety of gate level simulators.

DataSheet Pro DataSheet Pro provides documentation professionals with a more efficient environment for the management of documents containing multiple timing diagrams. Features include Object Linking and Embedding (OLE) to provide immediate in-place editing of timing diagrams, style sheet support, image view support, web-ready image generation, project management, and support for the industry-standard Timing Diagram Markup Language (TDML) format.

For the budget conscious engineer, we provide Timing Diagrammer Pro, a powerful, feature-laden timing diagram editor with an unbeatable price. Analyze your design in the early stages, before you have a schematic. Perform true full-range min/max timing analysis to eliminate all timing violations and race conditions. Timing Diagrammer Pro automatically calculates critical paths and adjusts for reconvergent fanout. Inserting diagrams into word processors is painless, thanks to a variety of image capture formats.



SynaptiCAD products are Year 2000 Compliant

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Phone: 540-953-3390 | Email: sales@syncad.com | Fax: 540-953-3078


Copyright 1999, SynaptiCAD Inc., All rights reserved. Timing Diagrammer Pro, WaveFormer Pro, TestBencher Pro, VeriLogger Pro, DataSheet Pro and SynaptiCAD are trademarks of SynaptiCAD, Inc. All other marks are trademarks of their respective owners.

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