TestBencher Pro

A self-testing, multi-diagram
test bench generator for VHDL and Verilog

Surveys of HDL users have indicated that the generation of complex HDL test benches typically consumes 35% of the entire front-end ASIC design cycle. In an effort to reduce test bench creation time SynaptiCAD has released its newest product, TestBencher Pro, a self-testing test bench generator for VHDL and Verilog based on SynaptiCAD's previous product, WaveFormer. Test benches generated by TestBencher Pro include input stimulus vectors and extra code that checks simulation output for correctness. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. Using TestBencher Pro, bus-functional microprocessor interfaces can be modeled with only a few lines of code. TestBencher Pro also provides an automated method for checking large ASIC simulation runs.


TestBencher Pro features

  • Customizable generation of self-testing test benches
  • Multi-diagram test benches
  • Automatic signal generation from a Boolean equation of other signals
  • Automatic signal generation from a temporal equation
  • Timing diagram analysis
  • Export to popular desktop publishing programs and word processors


Got a question about TestBencher Pro and HDLs?

Post your question on the newsgroup comp.lang.verilog and it will be answered by our technical support staff (the newsgroup is checked at least once a day). You can always call 800-804-7073 to have any questions answered directly.




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Copyright 1999, SynaptiCAD Inc., All rights reserved. Timing Diagrammer Pro, WaveFormer Pro, TestBencher Pro, VeriLogger Pro, DataSheet Pro and SynaptiCAD are trademarks of SynaptiCAD, Inc. All other marks are trademarks of their respective owners.
SynaptiCAD Inc. | PO Box 10608 Blacksburg, VA 24062-0608 | 540 953-3390 | sales@syncad.com

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